Semiconductor devices are used in a large number of electronic devices such as computers, cell phones and others. One of the goals of the semiconductor industry is to continue shrinking the size and increasing the speed of individual devices. Smaller devices can operate at higher speeds since the physical distance between components is smaller. In addition, higher conductivity materials such as copper are replacing lower conductivity materials such as aluminum. One other challenge is to increase the mobility of semiconductor carriers such as electrons and holes.
One technique to improve transistor performance is to strain (i.e., distort) the semiconductor crystal lattice near the charge-carrier channel region. Transistors built on strained silicon, for example, have greater charge-carrier mobility than those fabricated using conventional substrates. One technique to strain silicon is to provide a layer of germanium or silicon germanium. A thin layer of silicon may be grown over the germanium-containing layer. Since the germanium crystal lattice is larger than silicon, the germanium-containing layer creates a lattice mismatch stress in adjacent layers. Strained channel transistors may then be formed in the strained silicon layer.
Another technique is to provide a stress layer over the transistor. Variants of stress layers can be used for mobility and performance boost of devices. For example, stress can be provided by a contact etch stop layer (CESL), single layers, dual layers, stress memory transfer layers, and STI liners. Most of these techniques use nitride layers to provide tensile and compressive stresses, however other materials can be used in other applications, e.g., HDP oxide layers.
In other applications, SiGe can be utilized. For example, a silicon layer can be formed over a SiGe layer. Due to the different lattice structures, the SiGe will impart a strain onto the silicon layer. This strained silicon layer can be utilized to fabricate faster transistors. FIGS. 1a-1c provide examples of conventional stress-inducing layers. In each case, an n-channel transistor 10 and a p-channel transistor 12 are formed in a silicon substrate 14. Due to differences in electron and hole mobility for n-channel or p-channel transistors respectively, it is desirable to cause a compressive stress in the p-channel transistor 12 and a tensile stress in the n-channel transistor 10.
FIGS. 1a and 1b provide an example that uses a single layer 16 that can induce a tensile stress. Since the tensile stress will adversely affect the p-channel transistors, the layer is etched away in the example of FIG. 1a. In the example of FIG. 1b, the layer is amorphized (e.g., with a germanium implant) to relax or dissolve the stress in the portions of the layer 16 overlying the p-channel transistor 12. These two embodiments have the disadvantage that only the n-channel transistor 10 is strained.
FIG. 1c shows an example of a structure that includes a dual layer. In this case, a tensile stress inducing layer 16 is formed over the n-channel transistor 10 and a compressive stress inducing layer 18 is formed over the p-channel transistor 12. As an example, U.S. Pat. No. 6,573,173 discloses an implementation where first and second nitride layers are formed over the PMOS and NMOS transistors using first and second plasma-enhanced chemical vapor deposition (PECVD) processes, respectively. The first deposition provides a tensile nitride film to impart a compressive stress in the channel region of the PMOS device, in turn, increasing the PMOS carrier mobility. The tensile film is removed from over the NMOS device, and the second deposition then provides a compressive nitride film over the NMOS transistor. This compressive film is removed from over the PMOS device, but remains over the NMOS so as to induce a tensile stress in the NMOS channel region.
Another method of inducing strain into the transistor utilizes a modified shallow trench isolation (STI) region. One method includes lining a STI recess with a stressor before filling the recess with a dielectric. The stressor can then impart a stress onto the adjacent semiconductor.
A problem with conventional stress-inducing structures and methods is integrating them with existing CMOS manufacturing methods. This stems from the fundamentally different requirements for enhancing PMOS versus NMOS performance. A tensile channel stress is most effective for NMOS devices, while a compressive channel stress is most effective for PMOS devices. These distinct requirements burden semiconductor manufacturing, particularly CMOS manufacturing, because NMOS and PMOS devices each demands separate methods, steps, or materials.